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rev. 0.2 / feb. 2010 1 204pin ddr3 sdram sodimm *hynix semiconductor reserves th e right to change products or specifications without notice. ddr3 sdram unbuffered sodimms based on 2gb b-die HMT312S6BFR6C hmt325s6bfr6c hmt325s6bfr8c hmt351s6bfr8c www.datasheet.co.kr datasheet pdf - http://www..net/
rev. 0.2 / feb. 2010 2 revision history revision no. history draft date remark 0.1 initial release dec.2009 preliminary 0.2 added idd speciricaion feb.2010 preliminary www.datasheet.co.kr datasheet pdf - http://www..net/
rev. 0.2 / feb. 2010 3 description hynix unbuffered ddr3 sdram dimms (unbuffered doub le data rate synchronous dram dual in-line memory modules) are low power, high-speed oper ation memory modules that use hynix ddr3 sdram devices. these unbuffered ddr3 sdram dimms are inte nded for use as main memory when installed in systems such as mobile personal computers. features * this product is in compliance with the rohs directive. ordering information part number density organization component composition # of ranks HMT312S6BFR6C-g7/h9/pb 1gb 128mx64 128mx16(h5tq2g63bfr)*4 1 hmt325s6bfr6c-g7/h9/pb 2gb 256mx64 128mx16(h5tq2g63bfr)*8 2 hmt325s6bfr8c-g7/h9/pb 2gb 256mx64 256mx8(h5tq2g83bfr)*8 hmt351s6bfr8c-g7/h9/pb 4gb 512mx64 256mx8(h5tq2g83bfr)*16 2 ? vdd=1.5v +/- 0.075v ? vddq=1.5v +/- 0.075v ? vddspd=3.0v to 3.6v ? functionality and operations comply with the ddr3 sdram datasheet ? 8 internal banks ? data transfer rates: pc3-10600, pc3-8500, or pc3-6400 ? bi-directional differential data strobe ? 8 bit pre-fetch ? burst length (bl) switch on-the-fly: bl 8 or bc (burst chop) 4 ? on die termination (odt) supported ? rohs compliant www.datasheet.co.kr datasheet pdf - http://www..net/
rev. 0.2 / feb. 2010 4 key parameters speed grade address table mt/s grade tck (ns) cas latency (tck) trcd (ns) trp (ns) tras (ns) trc (ns) cl-trcd-trp ddr3-1066 -g7 1.875 7 13.125 13.125 37.5 50.625 7-7-7 ddr3-1333 -h9 1.5 9 13.5 13.5 36 49.5 9-9-9 ddr3-1600 -pb 1.25 11 13.75 13.75 35 48.75 11-11-11 grade frequency [mhz] remark cl6 cl7 cl8 cl9 cl10 cl11 -g7 800 1066 1066 -h9 800 1066 1066 1333 1333 -pb 800 1066 1066 1333 1333 1600 1gb(1rx16) 2gb(2rx16) 2gb(1rx8) 4gb(2rx8) refresh method 8k/64ms 8k/64ms 8k/64ms 8k/64ms row address a0-a13 a0-a13 a0-a14 a0-a14 column address a0-a9 a0-a9 a0-a9 a0-a9 bank address ba0-ba2 ba0-ba2 ba0-ba2 ba0-ba2 page size 2kb 2kb 1kb 1kb www.datasheet.co.kr datasheet pdf - http://www..net/
rev. 0.2 / feb. 2010 5 pin descriptions pin name description num ber pin name description num ber ck[1:0] clock input, positive line 2 dq[63:0] data input/output 64 ck [1:0] clock input, negative line 2 dm[7:0] data masks 8 cke[1:0] clock enables 2 dqs[7:0] data strobes 8 ras row address strobe 1 dqs [7:0] data strobes, negative line 8 cas column address strobe 1 event temperature event pin 1 we write enable 1 test logic analyzer specific test pin (no connect on sodimm) 1 s [1:0] chip selects 2 reset reset pin 1 a[9:0],a11, a[15:13] address inputs 14 v dd core and i/o power 18 a10/ap address input/autoprecharge 1 v ss ground 52 a12/bc address input/burst chop 1 ba[2:0] sdram bank addresses 3 v refdq input/output reference 1 odt[1:0] on die termination inputs 2 v refca 1 scl serial presence detect (spd) clock input 1 v tt termination voltage 2 sda spd data input/output 1 v ddspd spd power 1 sa[1:0] spd address inputs 2 nc reserved for future use 2 total: 204 www.datasheet.co.kr datasheet pdf - http://www..net/
rev. 0.2 / feb. 2010 6 input/output functional descriptions symbol type polarity function ck0/ck0 ck1/ck1 in cross point the system clock inputs. all address and co mmand lines are sample d on the cross point of the rising edge of ck and falling edge of ck . a delay locked loop (dll) circuit is driven from the clock inputs and output timing for read operations is synchronized to the input clock. cke[1:0] in active high activates the ddr3 sdram ck signal when high and deactivates the ck signal when low. by deactivating the clocks, cke low initiates the power down mode or the self refresh mode. s [1:0] in active low enables the associated ddr3 sdram command decoder when low and disables the command decoder when high. when the co mmand decoder is disabled, new commands are ignored but previous operations continue. rank 0 is selected by s0 ; rank 1 is selected by s1 . odt[1:0] in active high asserts on-die termination for dq, dm, dqs, and dqs signals if enabled via the ddr3 sdram mode register. r as , cas , we in active low when sampled at the cross point of the rising edge of ck, signals cas , ras , and we define the operation to be executed by the sdram. v refdq v refca supply reference voltage for sstl15 inputs. ba[2:0] in ? selects which sdram internal bank of eight is activated. a[9:0], a10/ap, a11, a12/bc a[15:13] in ? during a bank activate command cycle, defines the row address when sampled at the cross point of the rising edge of ck and falling edge of ck . during a read of write com- mand cycle, defines the column address when sampled at the cross point of the rising edge of ck and falling edge of ck . in addition to the column address, ap is used to invoke autoprecharge operation at the end of th e burst read or write cycle. if ap is high autoprecharge is selected and ba0-ban defines the bank to be precharged. if ap is low, autoprecharge is disabled. duri ng a precharge command cycle, ap is used in conjunction with ba0-ban to control which bank(s) to precharge. if ap is high, all banks will be pre- charged regardless of the state of ba0-ban inputs. if ap is low, then ba0-ban are used to define which bank to precharge. a12(bc ) is samples during read and write com- mands to determine if burst chop (on-the-fl y) will be performed (high, no burst chop: low, burst chopped). dq[63:0] i/o ? data input/output pins. dm[7:0] in active high the data write masks, associated with one da ta byte. in write mode , dm operates as a byte mask by allowing input data to be written if it is low but blocks the write operation if it is high. in read mode, dm lines have no effect. v dd , v ddspd v ss supply power supplies for core, i/o, serial presence detect, and ground for the module. dqs[7:0], dqs[7:0] i/o cross point the data strobes, associated with one data byte, sourced with data transfers. in write mode, the data strobe is sourced by the cont roller and is centered in the data window. in read mode, the data strobe is sourced by the ddr3 sdrams and is sent at the lead- ing edge of the data window. dqs signals are complements, and timing is relative to the crosspoint of respective dqs and dqs . sa[1:0] in ? these signals are tied at the system planar to either v ss or v ddspd to configure the serial spd eeprom address range. www.datasheet.co.kr datasheet pdf - http://www..net/
rev. 0.2 / feb. 2010 7 sda i/o ? this bidirectional pin is used to transfer data into or out of the spd eeprom. a resistor must be connected from the sda bus line to v ddspd on the system pl anar to act as a pullup. scl in ? this signal is used to clock data into and out of the spd eeprom. a resistor may be con- nected from the scl bus time to v ddspd on the system planar to act as a pullup. event out (open drain) active low this signal indicates that a thermal event has been detected in the thermal sensing device.the system should guarantee the electrical level requirement is met for the event pin on ts/spd part. no pull-up resister is provided on dimm. v ddspd supply serial eeprom positive power supply wired to a separate power pin at the connector which supports from 3.0 volt to 3.6 volt (nominal 3.3v) operation. reset in the reset pin is connected to the reset pin on the register and to the reset pin on the dram. test used by memory bus analysis tools (unused (nc) on memory dimms) symbol type polarity function www.datasheet.co.kr datasheet pdf - http://www..net/
rev. 0.2 / feb. 2010 8 pin assignments pin # front side pin # back side pin # front side pin # back side pin # front side pin # back side pin # front side pin # back side 1 v ref dq 2 v ss 53 dq19 54 v ss 105 v dd 106 v dd 157 dq42 158 dq46 3 v ss 4 dq4 55 v ss 56 dq28 107 a10/ap 108 ba1 159 dq43 160 dq47 5 dq0 6 dq5 57 dq24 58 dq29 109 ba0 110 ras 161 v ss 162 v ss 7dq18 v ss 59 dq25 60 v ss 111 v dd 112 v dd 163 dq48 164 dq52 9 v ss 10 dqs 0 61 v ss 62 dqs 3 113 we 114 s 0 165 dq49 166 dq53 11 dm0 12 dqs0 63 dm3 64 dqs3 115 cas 116 odt0 167 v ss 168 v ss 13 v ss 14 v ss 65 v ss 66 v ss 117 v dd 118 v dd 169 dqs 6 170 dm6 15 dq2 16 dq6 67 dq26 68 dq30 119 a13 2 120 odt1 171 dqs6 172 v ss 17 dq3 18 dq7 69 dq27 70 dq31 121 s 1 122 nc 173 v ss 174 dq54 19 v ss 20 v ss 71 v ss 72 v ss 123 v dd 124 v dd 175 dq50 176 dq55 21 dq8 22 dq12 73 cke0 74 cke1 125 test 126 v ref ca 177 dq51 178 v ss 23 dq9 24 dq13 75 v dd 76 v dd 127 v ss 128 v ss 179 v ss 180 dq60 25 v ss 26 v ss 77 nc 78 a15 2 129 dq32 130 dq36 181 dq56 182 dq61 27 dqs 1 28 dm1 79 ba2 80 a14 2 131 dq33 132 dq37 183 dq57 184 v ss 29 dqs1 30 reset 81 v dd 82 v dd 133 v ss 134 v ss 185 v ss 186 dqs 7 31 v ss 32 v ss 83 a12/bc 84 a11 135 dqs 4 136 dm4 187 dm7 188 dqs7 33 dq10 34 dq14 85 a9 86 a7 137 dqs4 138 v ss 189 v ss 190 v ss 35 dq11 36 dq15 87 v dd 88 v dd 139 v ss 140 dq38 191 dq58 192 dq62 37 v ss 38 v ss 89 a8 90 a6 141 dq34 142 dq39 193 dq59 194 dq63 39 dq16 40 dq20 91 a5 92 a4 143 dq35 144 v ss 195 v ss 196 v ss 41 dq17 42 dq21 93 v dd 94 v dd 145 v ss 146 dq44 197 sa0 198 event 43 v ss 44 v ss 95 a3 96 a2 147 dq40 148 dq45 199 vdd spd 200 sda 45 dqs 2 46 dm2 97 a1 98 a0 149 dq41 150 v ss 201 sa1 202 scl 47 dqs2 48 v ss 99 v dd 100 v dd 151 v ss 152 dqs 5 203 v tt 204 v tt 49 v ss 50 dq22 101 ck0 102 ck1 153 dm5 154 dqs5 51 dq18 52 dq23 103 ck0 104 ck1 155 v ss 156 v ss nc = no connect; rfu = reserved future use 1. test (pin 125) is reserved for bus analysis probes and is nc on normal memory modules. 2. this address might be connected to nc balls of the dram s (depending on density); ei ther way they will be con- nected to the termination resistor. www.datasheet.co.kr datasheet pdf - http://www..net/
rev. 0.2 / feb. 2010 9 functional block diagram 1gb, 128mx64 modu le(1rank of x16) dqs1 dqs1 dm1 dq [8:15] dqs0 dqs0 dm0 dq [0:7] ldqs ldqs ldm dq [0:7] d0 udqs udqs udm dq [8:15] a2 te m p s e n s o r sda d0?d3 v dd spd spd/ts d0?d3 v ref ca scl v tt d0?d3 v dd event ras cas s0 we ck0 ck0 cke0 odt0 a[o:n]/ba[o:n] 240ohm zq +/-1% dqs3 dqs3 dm3 dq [24:31] dqs2 dqs2 dm2 dq [16:23] ldqs ldqs ldm dq [0:7] d1 udqs udqs udm dq [8:15] ras cas cs we ck ck cke odt a[o:n]/ba[o:n] 240ohm zq +/-1% dqs5 dqs5 dm5 dq [40:47] dqs4 dqs4 dm4 dq [32:39] ldqs ldqs ldm dq [0:7] d2 udqs udqs udm dq [8:15] ras cas cs we ck ck cke odt a[o:n]/ba[o:n] 240ohm zq +/-1% dqs7 dqs7 dm7 dq [56:63] dqs6 dqs6 dm6 dq [48:55] ldqs ldqs ldm dq [0:7] d3 udqs udqs udm dq [8:15] ras cas cs we ck ck cke odt a[o:n]/ba[o:n] 240ohm zq +/-1% vtt vtt ras cas cs we ck ck cke odt a[o:n]/ba[o:n] vdd a1 a0 scl sa0 sa1 (with spd) event a2 sda scl wp a1 a0 scl sa0 sa1 (spd) v tt v ref dq v ss ck0 ck0 ck1 ck1 odt1 s1 event reset d0?d3, spd, temp sensor d0?d3 d0?d3 terminated at near card edge nc nc temp sensor d0-d3 d0 d1 d2 d3 vtt notes 1. dq wiring may differ from that shown however, dq, dm, dqs, and dqs relation- ships are maintained as shown address and control lines rank 0 the spd may be integrated with the temp sensor or may be a separate component www.datasheet.co.kr datasheet pdf - http://www..net/
rev. 0.2 / feb. 2010 10 2gb, 256mx64 modu le(2rank of x16) dqs1 dqs1 dm1 dq [8:15] dqs0 dqs0 dm0 dq [0:7] ldqs ldqs ldm dq [0:7] d0 udqs udqs udm dq [8:15] ras cas s0 we ck0 ck0 cke0 odt0 a[o:n]/ba[o:n] 240ohm zq +/-1% dqs3 dqs3 dm3 dq [24:31] dqs2 dqs2 dm2 dq [16:23] ldqs ldqs ldm dq [0:7] d1 udqs udqs udm dq [8:15] ras cas cs we ck ck cke odt a[o:n]/ba[o:n] 240ohm zq +/-1% dqs5 dqs5 dm5 dq [40:47] dqs4 dqs4 dm4 dq [32:39] ldqs ldqs ldm dq [0:7] d2 udqs udqs udm dq [8:15] ras cas cs we ck ck cke odt a[o:n]/ba[o:n] 240ohm zq +/-1% dqs7 dqs7 dm7 dq [56:63] dqs6 dqs6 dm6 dq [48:55] ldqs ldqs ldm dq [0:7] d3 udqs udqs udm dq [8:15] ras cas cs we ck ck cke odt a[o:n]/ba[o:n] 240ohm zq +/-1% vtt ras cas cs we ck ck cke odt a[o:n]/ba[o:n] vdd ldqs ldqs ldm dq [0:7] d4 udqs udqs udm dq [8:15] 240ohm zq +/-1% ras cas cs we ck ck cke odt a[o:n]/ba[o:n] ldqs ldqs ldm dq [0:7] d5 udqs udqs udm dq [8:15] 240ohm zq +/-1% ras cas cs we ck ck cke odt a[o:n]/ba[o:n] ldqs ldqs ldm dq [0:7] d6 udqs udqs udm dq [8:15] 240ohm zq +/-1% ras cas cs we ck ck cke odt a[o:n]/ba[o:n] ldqs ldqs ldm dq [0:7] d7 udqs udqs udm dq [8:15] 240ohm zq +/-1% ras cas cs we ck ck cke odt a[o:n]/ba[o:n] ck1 ck1 cke1 odt1 s1 vdd a2 te m p s e n s o r sda d0?d7 v dd spd spd/ts d0?d7 v ref ca scl v tt d0?d7 v dd event a1 a0 scl sa0 sa1 (with spd) event a2 sda scl wp a1 a0 scl sa0 sa1 (spd) v tt v ref dq v ss ck0 ck0 ck1 ck1 event reset d0?d7, spd, temp sensor d0?d3 d0?d7 temp sensor d0-d7 notes 1. dq wiring may differ from that shown however, dq, dm, dqs, and dqs relation- ships are maintained as shown address and control lines rank 0 the spd may be integrated with the temp sensor or may be a separate component d0?d3 d0?d7 d0 d1 d2 d3 vtt d4 d5 d6 d7 vtt v1 v2 v4 v3 v1 v2 v4 v3 rank 1 vtt vtt www.datasheet.co.kr datasheet pdf - http://www..net/
rev. 0.2 / feb. 2010 11 2gb, 256mx64 module( rank of x
dqs0 dqs0 dm0 dq[0:7] dqs dqs dm dq [0:7] d0 ras cas s0 we ck0 ck0 cke0 odt0 240ohm zq +/-1% ras cas cs we ck ck cke odt a[o:n]/ba[o:n] dqs dqs dm dq [0:7] d4 240ohm zq +/-1% ras cas cs we ck ck cke odt a[o:n]/ba[o:n] dqs2 dqs2 dm2 q [16:23] dqs dqs dm dq [0:7] d1 240ohm zq +/-1% ras cas cs we ck ck cke odt a[o:n]/ba[o:n] dqs dqs dm dq [0:7] d5 240ohm zq +/-1% ras cas cs we ck ck cke odt a[o:n]/ba[o:n] dqs4 dqs4 dm4 q [32:39] dqs dqs dm dq [0:7] d2 240ohm zq +/-1% ras cas cs we ck ck cke odt a[o:n]/ba[o:n] ldqs ldqs ldm dq [0:7] d6 240ohm zq +/-1% ras cas cs we ck ck cke odt a[o:n]/ba[o:n] dqs3 dqs3 dm3 q [48:55] dqs dqs dm dq [0:7] d3 240ohm zq +/-1% ras cas cs we ck ck cke odt a[o:n]/ba[o:n] ldqs ldqs ldm dq [0:7] d7 240ohm zq +/-1% ras cas cs we ck ck cke odt a[o:n]/ba[o:n] dqs1 dqs1 dm1 dq[8:15] dqs3 dqs3 dm3 dq[24:31] dqs5 dqs5 dm5 dq[40:47] dqs7 dqs7 dm7 dq[56:63] a2 te mp s e ns or sda d0?d7 v dd spd spd/ts d0?d7 v ref ca scl v tt d0?d7 v dd event a1 a0 scl sa0 sa1 (with spd) event a2 sda scl wp a1 a0 scl sa0 sa1 (spd) vtt v ref dq v ss ck0 ck1 ck0 ck1 s1 odt1 d0?d7, spd, temp sensor d0?d7 d0?d7 nc nc notes 1. dq wiring may differ from that shown however, dq, dm, dqs, and dqs relationships are maintained as shown address and control lines rank 0 the spd may be integrated with the temp sensor or may be a separate component d0 d1 d2 d3 vtt d4 d5 d6 d7 vtt v1 v2 v4 v3 v1 v2 v4 v3 cke1 event reset temp sensor d0-d7 nc terminated near card edge www.datasheet.co.kr datasheet pdf - http://www..net/
rev. 0.2 / feb. 2010 12 4gb, 512mx64 modu le(2rank of x8) dqs3 dqs3 dm3 dq[24:31] dqs dqs dm dq [0:7] d11 ras cas s1 we ck1 ck1 cke1 odt1 a[o:n]/ba[o:n ] 240ohm zq +/-1% vtt ras cas cs we ck ck cke odt a[o:n]/ba[o:n] ldqs ldqs ldm dq [0:7] d3 240ohm zq +/-1% ras cas cs we ck ck cke odt a[o:n]/ba[o:n] ck0 ck0 cke0 odt0 s0 a2 tem p s e ns o r sda d0?d15 v dd spd spd/ts d0?d15 v ref ca scl v tt d0?d15 v dd event a1 a0 scl sa0 sa1 (with spd) event a2 sda scl wp a1 a0 scl sa0 sa1 (spd) v tt v ref dq v ss ck0 ck0 ck1 ck1 cke0 cke1 d0?d15, spd, temp sensor d0?d7 d8?d15 d0-d7 d8-d15 notes 1. dq wiring may differ from that shown however, dq, dm, dqs, and dqs rela- tionships are maintained as shown rank 0 d0?d7 d8?d15 rank 1 dqs1 dqs1 dm1 dq[8:15] dqs dqs dm dq [0:7] d1 240ohm zq +/-1% ras cas cs we ck ck cke odt a[o:n]/ba[o:n] ldqs ldqs ldm dq [0:7] d9 240ohm zq +/-1% ras cas cs we ck ck cke odt a[o:n]/ba[o:n] dqs0 dqs0 dm0 dq[0:7] dqs dqs dm dq [0:7] d0 240ohm zq +/-1% ras cas cs we ck ck cke odt a[o:n]/ba[o:n] ldqs ldqs ldm dq [0:7] d8 240ohm zq +/-1% ras cas cs we ck ck cke odt a[o:n]/ba[o:n] dqs4 dqs4 dm4 dq[32:39] dqs6 dqs6 dm6 dq[48:55] dqs7 dqs7 dm7 dq[56:43] dqs5 dqs5 dm5 dq[40:47] vtt vtt vdd vdd cterm cterm d12 d4 dqs dqs dm dq [0:7] 240ohm zq +/-1% ras cas cs we ck ck cke odt a[o:n]/ba[o:n] dqs dqs dm dq [0:7] 240ohm zq +/-1% ras cas cs we ck ck cke odt a[o:n]/ba[o:n] d6 d14 dqs dqs dm dq [0:7] zq +/-1% ras cas cs we ck ck cke odt a[o:n]/ba[o:n] dqs dqs dm dq [0:7] zq +/-1% ras cas cs we ck ck cke odt a[o:n]/ba[o:n] 240ohm 240ohm d7 d15 dqs dqs dm dq [0:7] zq +/-1% ras cas cs we ck ck cke odt a[o:n]/ba[o:n] dqs dqs dm dq [0:7] zq +/-1% ras cas cs we ck ck cke odt a[o:n]/ba[o:n] 240ohm 240ohm dqs2 dqs2 dm2 dq[6:23] dqs dqs dm dq [0:7] d2 240ohm zq +/-1% ras cas cs we ck ck cke odt a[o:n]/ba[o:n] ldqs ldqs ldm dq [0:7] d10 240ohm zq +/-1% ras cas cs we ck ck cke odt a[o:n]/ba[o:n] d5 d13 dqs dqs dm dq [0:7] zq +/-1% ras cas cs we ck ck cke odt a[o:n]/ba[o:n] dqs dqs dm dq [0:7] zq +/-1% ras cas cs we ck ck cke odt a[o:n]/ba[o:n] 240ohm 240ohm s0 odt0 s1 odt1 event reset d0?d7 d8?d15 temp sensor d0-d15 d0?d7 d8?d15 the spd may be integrated with the temp sensor or may be a separate component d0 v1 v9 d1 d11 d2 d13 d4 d14 d15 d9 d8 d10 d3 d12 d5 d7 d6 vtt v1 v2 v3 v4 v5 v6 v8 v7 v6 v8 v7 v5 v9 v1 v4 v3 v2 www.datasheet.co.kr datasheet pdf - http://www..net/
rev. 0.2 / feb. 2010 13 absolute maximum ratings absolute maximum dc ratings notes: 1. stresses greater than those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operat ion of the device at these or any other conditions above those indicated in the operational sections of this specif ication is not implied. exposure to absolute maximum rat- ing conditions for extended pe riods may affect reliability. 2. storage temperature is the case surface temperature on the center/top side of the dram. for the measurement conditions, please refer to jesd51-2 standard. 3. vdd and vddq must be within 300mv of each other at all times; and vref must not be greater than 0.6xvddq,when vdd and vddq are less than 500mv; vref may be equal to or less than 300mv. dram component operat ing temperature range notes: 1. operating temperature toper is the case surface temperature on the center / top side of the dram. for mea- surement conditions, please refer to the jedec document jesd51-2. 2. the normal temperature range specifies the temperatures where all dram specificatio ns will be supported. dur- ing operation, the dram case temperature must be maintained between 0 - 85 o c under all operating conditions. 3. some applications require operation of the dr am in the extended temperature range between 85 o c and 95 o c case temperature. full specifications are guaranteed in this range, but the following additional conditions apply: a. refresh commands must be doubled in frequency, theref ore reducing the refresh interval trefi to 3.9 s. it is also possible to specify a component with 1x refres h (trefi to 7.8s) in the extended temperature range. please refer to the dimm spd for option availability b. if self-refresh operation is required in the extended temperature range, then it is mandatory to either use the manual self-refresh mode with extended temperature range capability (mr2 a6 = 0b and mr2 a7 = 1b) or enable the optional auto self-refresh mode (mr2 a6 = 1b and mr2 a7 = 0b). hynix ddr3 sdrams sup- port auto self-refresh and extended temperature ra nge and please refer to hynix component datasheet and/or the dimm spd for trefi requirements in the extended temperature range. absolute maximum dc ratings symbol parameter rating units notes vdd voltage on vdd pin relative to vss - 0.4 v ~ 1.975 v v 1, vddq voltage on vddq pin relative to vss - 0.4 v ~ 1.975 v v 1, v in , v out voltage on any pin relative to vss - 0.4 v ~ 1.975 v v 1 t stg storage temperature -55 to +100 o c1, 2 temperature range symbol parameter rating units notes t oper normal operating temperature range 0 to 85 o c 1,2 extended temperature range 85 to 95 o c1,3 www.datasheet.co.kr datasheet pdf - http://www..net/
rev. 0.2 / feb. 2010 14 ac & dc operating conditions recommended dc operating conditions notes: 1. under all conditions, vddq must be less than or equal to vdd. 2. vddq tracks with vdd. ac parameters ar e measured with vdd and vddq tied together. ac & dc input measurement levels ac and dc logic input levels for single-ended signals ac and dc input levels for single -ended command and address signals notes: 1. for input only pins except reset , vref = vrefca (dc). 2. refer to ?overshoot and undershoot specifications? on page 27. 3. the ac peak noise on v ref may not allow v ref to deviate from v refca(dc) by more than +/-1% vdd (for reference: approx. +/- 15 mv). 4. for reference: approx. vdd/2 +/- 15 mv. recommended dc operating conditions symbol parameter rating units notes min. typ. max. vdd supply voltage 1.425 1.500 1.575 v 1,2 vddq supply voltage for output 1.425 1.500 1.575 v 1,2 single ended ac and dc input levels for command and address symbol parameter ddr3-800/1066/1333/1600 unit notes min max vih.ca(dc100) dc input logic high vref + 0.100 vdd v 1 vil.ca(dc100) dc input logic low vss vref - 0.100 v 1 vih.ca(ac175) ac input logic high vref + 0.175 note2 v 1, 2 vil.ca(ac175) ac input logic low note2 vref - 0.175 v 1, 2 vih.ca(ac150) ac input logic high vref + 0.150 note2 v 1, 2 vil.ca(ac150) ac input logic low note2 vref - 0.150 v 1, 2 v refca(dc ) reference voltage for add, cmd inputs 0.49 * vdd 0.51 * vdd v 3, 4 www.datasheet.co.kr datasheet pdf - http://www..net/
rev. 0.2 / feb. 2010 15 ac and dc input levels for single-ended signals ddr3 sdram will support two vih/v il ac levels for ddr3-800 and ddr3-1066 as specified in the table below. ddr3 sdram will also support corresponding tds values (table 41 and table 47 in ? ddr3 device operation?) as well as derating tables in table 44 of ?ddr3 device operation? depending on vih/vil ac lev- els. notes: 1. vref = vrefdq (dc). 2. refer to ?overshoot and undershoot specifications? on page 27. 3. the ac peak noise on v ref may not allow v ref to deviate from v refdq(dc) by more than +/-1% vdd (for reference: approx. +/- 15 mv). 4. for reference: approx. vdd/2 +/- 15 mv. single ended ac and dc input levels for dq and dm symbol parameter ddr3-800/1066 ddr3-1333/1600 unit notes min max min max vih.ca(dc100) dc input logic high vref + 0.100 vdd vref + 0.100 vdd v 1 vil.ca(dc100) dc input logic low vss vref - 0.100 vss vref - 0.100 v 1 vih.ca(ac175) ac input logic high vref + 0.175 note2 - - v 1, 2 vil.ca(ac175) ac input logic lo w note2 vref - 0.175 - - v 1, 2 vih.ca(ac150) ac input logic high vref + 0.150 note2 vref + 0.150 note2 v 1, 2 vil.ca(ac150) ac input logic low note2 vr ef - 0.150 note2 vref - 0.150 v 1, 2 v refdq(dc ) reference voltage for dq, dm inputs 0.49 * vdd 0.51 * vdd 0.49 * vdd 0.51 * vdd v 3, 4 www.datasheet.co.kr datasheet pdf - http://www..net/
rev. 0.2 / feb. 2010 16 vref tolerances the dc-tolerance limits and ac-noise limits for the reference voltages vrefca and v refdq are illustrated in figure below. it shows a valid reference voltage v ref (t) as a function of time. (v ref stands for v refca and v refdq likewise). v ref (dc) is the linear average of v ref (t) over a very long period of time (e.g. 1 sec). this average has to meet the min/max requirements in the table ?different ial input slew rate definition? on page 22. further- more v ref (t) may temporarily deviate from v ref (dc) by no more than +/- 1% vdd. illustration of v ref(dc) tolerance and v ref ac-noise limits the voltage levels for setup and hold time measurements v ih(ac) , v ih(dc) , v il(ac) , and v il(dc) are depen- dent on v ref . ?v ref ? shall be understood as v ref(dc) , as defined in figure above. this clarifies that dc-variations of v ref affect the absolute voltage a sign al has to reach to achieve a valid high or low level and therefore the time to which se tup and hold is measured. system timing and voltage budgets need to account for v ref(dc) deviations from the optimum position within the data-eye of the input signals. this also clarifies that the dram setup/hold specific ation and derating values need to include time and voltage associated with v ref ac-noise. timing and voltage effects due to ac-noise on v ref up to the speci- fied limit (+/- 1% of vdd) are included in dram timings and their associated deratings. vdd vss vdd/2 v ref(dc) v ref ac-noise voltage time v ref(dc)max v ref(dc)min v ref (t) www.datasheet.co.kr datasheet pdf - http://www..net/
rev. 0.2 / feb. 2010 17 ac and dc logic input levels for differential signals differential signal definition definition of differential ac-swi ng and ?time above ac-level? t dvac time differential input voltage(i.e.dqs - dqs#, ck - ck#) v il.diff.ac.max v il.diff.max 0 v il.diff.min v il.diff.ac.min t dvac half cycle t dvac www.datasheet.co.kr datasheet pdf - http://www..net/
rev. 0.2 / feb. 2010 18 differential swing requirem ents for clock (ck - ck ) and strobe (dqs-dqs ) notes: 1. used to define a differential signal slew-rate. 2. for ck - ck use vih/vil (ac) of aadd/cmd and vrefca; for dqs - dqs , dqsl, dqsl , dqsu, dqsu use vih/vil (ac) of dqs and vrefdq; if a reduced ac-high or ac-low le vels is used for a signal group, then the reduced level applies also here. 3. these values are not defined; however, the single-ended signals ck, ck , dqs, dqs , dqsl, dqsl , dqsu, dqsu need to be within the respective limits (vih (dc) max, vil (dc) min) for sing le-ended signals as well as the limita- tions for overshoot and undershoot. refer to ?overs hoot and undershoot specifications? on page 27. differential ac and dc input levels symbol parameter ddr3-800, 1066, 1333, & 1600 unit notes min max vihdiff differential input high + 0.200 note 3 v 1 vildiff differential input logic low note 3 - 0.200 v 1 vihdiff (ac) differential input high ac 2 x (vih (ac) - vref) note 3 v 2 vildiff (ac) differential input low ac note 3 2 x (vil (ac) - vref) v 2 allowed time before ringback (tdvac) for ck - ck and dqs - dqs slew rate [v/ns] tdvac [ps] @ |vih/ldiff (ac)| = 350mv tdvac [ps] @ |vih/ldiff (ac)| = 300mv min max min max > 4.0 75 - 175 - 4.0 57 - 170 - 3.0 50 - 167 - 2.0 38 - 163 1.8 34 - 162 - 1.6 29 - 161 - 1.4 22 - 159 - 1.2 13 - 155 - 1.0 0 - 150 - < 1.0 0 - 150 - www.datasheet.co.kr datasheet pdf - http://www..net/
rev. 0.2 / feb. 2010 19 single-ended requirements for differential signals each individual component of a differen tial signal (ck, dqs, dqsl, dqsu, ck , dqs , dqsl , of dqsu ) has also to comply with certain requ irements for single-ended signals. ck and ck have to approximately reach vsehmin / vselmax (approximately equal to the ac-levels (vih (ac) / vil (ac)) for add/cmd signals) in every half-cycle. dqs, dqsl, dqsu, dqs , dqsl have to reach vsehmin / vselmax (a pproximately the ac-levels (vih (ac) / vil (ac)) for dq signals) in every half-cyc le preceding and following a valid transition. note that the applicable ac-levels for add/cmd and dq ?s might be different per speed-bin etc. e.g., if vih.ca(ac150)/vil.ca(ac150) is used for add/cmd signal s, then these ac-levels apply also for the single- ended signals ck and ck . single-ended requirements for differential signals. note that, while add/cmd and dq signal requirements are with respect to vref, the single-ended compo- nents of differential signals have a requirement with respect to vdd / 2; this is nominally the same. the transition of single-ended signals through the ac-lev els is used to measure se tup time. for single-ended components of differential signals the requirement to reach vselmax, vsehmin ha s no bearing on timing, but adds a restriction on the common mode characteristics of these signals. vdd or vddq vsehmin vdd/2 or vddq/2 vseh vselmax vss or vssq ck or dqs vsel time www.datasheet.co.kr datasheet pdf - http://www..net/
rev. 0.2 / feb. 2010 20 notes: 1. for ck, ck use vih/vil (ac) of add/cmd; for strobes (dqs, dqs , dqsl, dqsl , dqsu, dqsu ) use vih/vil (ac) of dqs. 2. vih (ac)/vil (ac) for dqs is based on vrefdq; vih (ac) /vil (ac) for add/cmd is based on vrefca; if a reduced ac-high or ac-low level is used for a signal gr oup, then the reduced level applies also here. 3. these values are not defined; however, the single-ended signals ck, ck , dqs, dqs , dqsl, dqsl , dqsu, dqsu need to be within the respective limits (vih (dc) max, vil (dc) min) for sing le-ended signals as well as the limita- tions for overshoot and undershoot. refer to ?overs hoot and undershoot specifications? on page 27. differential input cross point voltage to guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe, each cross point voltage of differential input signals (ck, ck and dqs, dqs ) must meet the requirements in the table below. the differential inpu t cross point voltage vix is measured from the actual cross point of true and complement signal s to the midlevel between of vdd and vss vix definition single-ended levels for ck, dqs, dqsl, dqsu, ck , dqs , dqsl or dqsu symbol parameter ddr3-800, 1066, 1333, & 1600 unit notes min max vseh single-ended high level for strobes (vdd / 2) + 0.175 note 3 v 1,2 single-ended high level for ck, ck (vdd /2) + 0.175 note 3 v 1,2 vsel single-ended low level for strobes note 3 (vdd / 2) = 0.175 v 1,2 single-ended low level for ck, ck note 3 (vdd / 2) = 0.175 v 1,2 vdd vss vdd/2 v ix v ix v ix ck , dqs ck, dqs www.datasheet.co.kr datasheet pdf - http://www..net/
rev. 0.2 / feb. 2010 21 notes: 1. extended range for v ix is only allowed for clock and if sing le-ended clock input signals ck and ck are monotonic with a single-ended swing vsel / vseh of at least vdd/2 +/-250 mv, and when the differential slew rate of ck - ck is larger than 3 v/ns. 2. refer to the table ?single-ended levels for ck, dqs, dqsl, dqsu, ck, dqs, dqsl or dqsu? on page 20 for vsel and vseh standard values. slew rate definitions for single-ended input signals see 7.5 ?address / command setup, hold and derating ? on page 137 in ?ddr3 device operation? for sin- gle-ended slew rate definitions for address and command signals. see 7.6 ?data setup, hold and slew rate derating? on page 144 in ?ddr3 device operation? for single- ended slew rate definition for data signals. cross point voltage for differential input signals (ck, dqs) symbol parameter ddr3-800, 1066, 1333, & 1600 unit notes min max v ix differential input cross point voltage relative to vdd/2 for ck, ck -150 150 mv -175 175 mv 1 v ix differential input cross point voltage relative to vdd/2 for dqs, dqs -150 150 mv www.datasheet.co.kr datasheet pdf - http://www..net/
rev. 0.2 / feb. 2010 22 slew rate definitions for differential input signals input slew rate for differential signals (ck, ck and dqs, dqs ) are defined and measur ed as shown in table and figure below. notes: the differential signal (i.e. ck-ck and dqs-dqs ) must be linear between these thresholds. differential input slew rate definition for dqs, dqs and ck, ck differential input slew rate definition description measured defined by min max differential input slew rate for rising edge (ck-ck and dqs-dqs ) vildiffmax vihdiffmin [vihdiffmi n-vildiffmax] / deltatrdiff differential input slew rate for falling edge (ck-ck and dqs-dqs ) vihdiffmin vildiffmax [vihdiffmi n-vildiffmax] / deltatfdiff delta tfdiff delta trdiff vihdiffmin vildiffmax 0 differential input voltag e (i.e. dqs-dqs; ck-ck) differential input slew rate definition for dqs, dqs# and ck, ck# www.datasheet.co.kr datasheet pdf - http://www..net/
rev. 0.2 / feb. 2010 23 ac & dc output measurement levels single ended ac and dc output levels table below shows the output levels used for measurements of single ended signals. notes: 1. the swing of ? 1 x v ddq is based on approximately 50% of the st atic single ended output high or low swing with a driver impedance of 40 ? and an effective test load of 25 ? to v tt = v ddq / 2. differential ac and dc output levels table below shows the output levels used for measurements of single ended signals. notes: 1. the swing of ? x v ddq is based on approximately 50% of the st atic differential output high or low swing with a driver impedance of 40 ? and an effective test load of 25 ? to v tt = v ddq /2 at each of the differential outputs. single-ended ac and dc output levels symbol parameter ddr3-800, 1066, 1333 and 1600 unit notes v oh(dc) dc output high measurement level (for iv curve linearity) 0.8 x v ddq v v om(dc) dc output mid measurement level (for iv curve linearity) 0.5 x v ddq v v ol(dc) dc output low measurement le vel (for iv curve linearity) 0.2 x v ddq v v oh(ac) ac output high measurement level (for output sr) v tt + 0.1 x v ddq v1 v ol(ac) ac output low measurement level (for output sr) v tt - 0.1 x v ddq v1 differential ac and dc output levels symbol parameter ddr3-800, 1066, 1333 and 1600 unit notes v ohdiff (ac) ac differential output high measurement level (for output sr) + 0.2 x v ddq v1 v oldiff (ac) ac differential output low measurement level (for output sr) - 0.2 x v ddq v1 www.datasheet.co.kr datasheet pdf - http://www..net/
rev. 0.2 / feb. 2010 24 single ended ou tput slew rate when the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between v ol(ac) and v oh(ac) for single ended signals are sh own in table and figure below. notes: 1. output slew rate is verified by design and charac terisation, and may not be su bject to production test. single ended output slew rate definition description: sr; slew rate q: query output (like in dq, which stands for data-in, query-output) se: single-ended signals for ron = rzq/7 setting single-ended output slew rate definition description measured defined by from to single-ended output slew rate for rising edge v ol(ac) v oh(ac) [v oh(ac) -v ol(ac) ] / deltatrse single-ended output slew rate for falling edge v oh(ac) v ol(ac) [v oh(ac) -v ol(ac) ] / deltatfse output slew rate (single-ended) ddr3-800 ddr3-1066 ddr3-1333 ddr3-1600 units parameter symbol min max min max min max min max single-ended output slew rate srqse 2.5 5 2.5 5 2.5 5 tbd 5 v/ns delta tfse delta trse voh(ac) vol(ac) v ? single ended output voltage(l.e.dq) single ended output slew rate definition www.datasheet.co.kr datasheet pdf - http://www..net/
rev. 0.2 / feb. 2010 25 differential output slew rate with the reference load for timing measurements, output slew rate for falling an d rising edges is defined and measured between voldiff (ac) and vohdiff (ac) fo r differential signals as shown in table and figure below. differential output slew rate definition differential output slew rate definition description measured defined by from to differential output slew rate for rising edge v oldiff (ac) v ohdiff (ac) [v ohdiff (ac) -v oldiff (ac) ] / deltatrdiff differential output slew rate for falling edge v ohdiff (ac) v oldiff (ac) [v ohdiff (ac) -v oldiff (ac) ] / deltatfdiff notes: 1. output slew rate is verified by design and charac terization, and may not be subject to production test. differential output slew rate ddr3-800 ddr3-1066 ddr3-1333 ddr3-1600 units parameter symbol min max min max min max min max differential output slew rate srqdiff 5 10 5 10 5 10 tbd 10 v/ns description: sr; slew rate q: query output (like in dq, which stands for data-in, query-output) se: single-ended signals for ron = rzq/7 setting delta tfdiff delta trdiff vohdiff(ac) voldiff(ac) o differential output voltage(i.e. dqs-dqs) differential output slew rate definition www.datasheet.co.kr datasheet pdf - http://www..net/
rev. 0.2 / feb. 2010 26 reference load for ac timing and output slew rate figure below represents the effective reference load of 25 ohms used in defining the relevant ac timing parameters of the device as well as output slew rate measurements. it is not intended as a precise representation of an y particular system environment or a depiction of the actual load presented by a production tester. system de signers should use ibis or other simulation tools to correlate the timing reference load to a system environment. manufacturers correlate to their production test conditions, generally one or more coaxial transm ission lines terminated at the tester electronics. reference load for ac timing and output slew rate dut dq dqs dqs vddq 25 ohm vtt = vddq/2 ck, ck www.datasheet.co.kr datasheet pdf - http://www..net/
rev. 0.2 / feb. 2010 27 overshoot and unders hoot specifications address and control overshoot and undershoot specifications address and control overshoo t and undershoot definition ac overshoot/undershoot specification for address and control pins parameter ddr3- 800 ddr3- 1066 ddr3- 1333 ddr3- 1600 units maximum peak amplitude allowed for overshoo t area. (see figure below) 0.4 0.4 0.4 0.4 v maximum peak amplitude allowed for undershoot area. (see figure below) 0.4 0.4 0.4 0.4 v maximum overshoot area above vdd (see figure below) 0.67 0.5 0.4 0.33 v-ns maximum undershoot area below vss (see figure below) 0.67 0.5 0.4 0.33 v-ns (a0-a15, ba0-ba3, cs , ras , cas , we , cke, odt) see figure below for each parameter definition maximum amplitude overshoot area vdd vss maxim um am plitude undershoot area time (ns) address and control overshoot and undershoot definition volts (v) www.datasheet.co.kr datasheet pdf - http://www..net/
rev. 0.2 / feb. 2010 28 clock, data, strobe and mask over shoot and undershoot specifications clock, data, strobe and mask ov ershoot and undershoot definition ac overshoot/undershoot specificatio n for clock, data, strobe and mask parameter ddr3- 800 ddr3- 1066 ddr3- 1333 ddr3- 1600 units maximum peak amplitude allowed for overshoot area. (see figure below) 0.4 0.4 0.4 0.4 v maximum peak amplitude allowed for undershoo t area. (see figure below) 0.4 0.4 0.4 0.4 v maximum overshoot area above vdd (see figure below) 0.25 0.19 0.15 0.13 v-ns maximum undershoot area below vss (see figure below) 0.25 0.19 0.15 0.13 v-ns (ck, ck , dq, dqs, dqs , dm) see figure below for each parameter definition maximum amplitude overshoot area vddq vssq maximum amplitude undershoot area time (ns) clock, data strobe and mask overshoot and undershoot definition volts (v) www.datasheet.co.kr datasheet pdf - http://www..net/
rev. 0.2 / feb. 2010 29 refresh parameters by device density refresh parameters by device density parameter rtt_nom setting 512mb 1gb 2gb 4gb 8gb units ref command act or ref command time trfc 90 110 160 300 350 ns average periodic refresh interval trefi 0 c 85 c 7.8 7.8 7.8 7.8 7.8 us 85 c < 95 c 3.9 3.9 3.9 3.9 3.9 us www.datasheet.co.kr datasheet pdf - http://www..net/
rev. 0.2 / feb. 2010 30 standard speed bins ddr3 sdram standard speed bins include tck, trcd , trp, tras and trc for each corresponding bin. ddr3-800 speed bins for specific notes see ?speed bin table notes? on page 34. speed bin ddr3-800e unit notes cl - nrcd - nrp 6-6-6 parameter symbol min max internal read command to first data t aa 15 20 ns act to internal read or write delay time t rcd 15 ? ns pre command period t rp 15 ? ns act to act or ref command period t rc 52.5 ? ns act to pre command period t ras 37.5 9 * trefi ns cl = 5 cwl = 5 t ck(avg) reserved ns 1, 2, 3, 4 cl = 6 cwl = 5 t ck(avg) 2.5 3.3 ns 1, 2, 3 supported cl settings 6 n ck supported cwl settings 5 n ck www.datasheet.co.kr datasheet pdf - http://www..net/
rev. 0.2 / feb. 2010 31 ddr3-1066 speed bins for specific notes see ?speed bin table notes? on page 34. speed bin ddr3-1066f unit note cl - nrcd - nrp 7-7-7 parameter symbol min max internal read command to first data t aa 13.125 20 ns act to internal read or write delay time t rcd 13.125 ? ns pre command period t rp 13.125 ? ns act to act or ref command period t rc 50.625 ? ns act to pre command period t ras 37.5 9 * trefi ns cl = 5 cwl = 5 t ck(avg) reserved ns 1, 2, 3, 4, 5 cwl = 6 t ck(avg) reserved ns 4 cl = 6 cwl = 5 t ck(avg) 2.5 3.3 ns 1, 2, 3, 5 cwl = 6 t ck(avg) reserved ns 1, 2, 3, 4 cl = 7 cwl = 5 t ck(avg) reserved ns 4 cwl = 6 t ck(avg) 1.875 < 2.5 ns 1, 2, 3, 4 cl = 8 cwl = 5 t ck(avg) reserved ns 4 cwl = 6 t ck(avg) 1.875 < 2.5 ns 1, 2, 3 supported cl settings 6, 7, 8 n ck supported cwl settings 5, 6 n ck www.datasheet.co.kr datasheet pdf - http://www..net/
rev. 0.2 / feb. 2010 32 ddr3-1333 speed bins for specific notes see ?speed bin table notes? on page 34. speed bin ddr3-1333h unit note cl - nrcd - nrp 9-9-9 parameter symbol min max internal read command to first data t aa 13.5 (13.125) 8 20 ns act to internal read or write delay time t rcd 13.5 (13.125) 8 ?ns pre command period t rp 13.5 (13.125) 8 ?ns act to act or ref command period t rc 49.5 (49.125) 8 ?ns act to pre command period t ras 36 9 * trefi ns cl = 5 cwl = 5 t ck(avg) reserved ns 1,2, 3,4, 6 cwl = 6, 7 t ck(avg) reserved ns 4 cl = 6 cwl = 5 t ck(avg) 2.5 3.3 ns 1, 2, 3, 6 cwl = 6 t ck(avg) reserved ns 1, 2, 3, 4, 6 cwl = 7 t ck(avg) reserved ns 4 cl = 7 cwl = 5 t ck(avg) reserved ns 4 cwl = 6 t ck(avg) 1.875 < 2.5 ns 1, 2, 3, 4, 6 reserved cwl = 7 t ck(avg) reserved ns 1, 2, 3, 4 cl = 8 cwl = 5 t ck(avg) reserved ns 4 cwl = 6 t ck(avg) 1.875 < 2.5 ns 1, 2, 3, 6 cwl = 7 t ck(avg) reserved ns 1, 2, 3, 4 cl = 9 cwl = 5, 6 t ck(avg) reserved ns 4 cwl = 7 t ck(avg) 1.5 <1.875 ns 1, 2, 3, 4 cl = 10 cwl = 5, 6 t ck(avg) reserved ns 4 cwl = 7 t ck(avg) 1.5 <1.875 ns 1, 2, 3 reserved ns supported cl settings 6, 8, (7), 9, (10) n ck supported cwl settings 5, 6, 7 n ck www.datasheet.co.kr datasheet pdf - http://www..net/
rev. 0.2 / feb. 2010 33 ddr3-1600 speed bins for specific notes see ?speed bin table notes? on page 34. speed bin ddr3-1600k unit note cl - nrcd - nrp 11-11-11 parameter symbol min max internal read command to first data t aa 13.75 (13.125) 8 20 ns act to internal read or write delay time t rcd 13.75 (13.125) 8 ?ns pre command period t rp 13.75 (13.125) 8 ?ns act to act or ref command period t rc 48.75 (48.125) 8 ?ns act to pre command period t ras 35 9 * trefi ns cl = 5 cwl = 5 t ck(avg) reserved ns 1, 2, 3, 4, 7 cwl = 6, 7 t ck(avg) reserved ns 4 cl = 6 cwl = 5 t ck(avg) 2.5 3.3 ns 1, 2, 3, 7 cwl = 6 t ck(avg) reserved ns 1, 2, 3, 4, 7 cwl = 7 t ck(avg) reserved ns 4 cl = 7 cwl = 5 t ck(avg) reserved ns 4 cwl = 6 t ck(avg) 1.875 < 2.5 ns 1, 2, 3, 4, 7 cwl = 7 t ck(avg) reserved ns 1, 2, 3, 4, 7 cwl = 8 t ck(avg) reserved ns 4 cl = 8 cwl = 5 t ck(avg) reserved ns 4 cwl = 6 t ck(avg) 1.875 < 2.5 ns 1, 2, 3, 7 cwl = 7 t ck(avg) reserved ns 1, 2, 3, 4, 7 cwl = 8 t ck(avg) reserved ns 1, 2, 3, 4 cl = 9 cwl = 5, 6 t ck(avg) reserved ns 4 cwl = 7 t ck(avg) 1.5 <1.875 ns 1, 2, 3, 4, 7 cwl = 8 t ck(avg) reserved ns 1, 2, 3, 4 cl = 10 cwl = 5, 6 t ck(avg) reserved ns 4 cwl = 7 t ck(avg) 1.5 <1.875 ns 1, 2, 3, 7 cwl = 8 t ck(avg) reserved ns 1,2,3,4 cl = 11 cwl = 5, 6,7 t ck(avg) reserved ns 4 cwl = 8 t ck(avg) 1.25 <1.5 ns 1, 2, 3 supported cl settings 6, (7), 8, (9), 10, 11 n ck supported cwl settings 5, 6, 7, 8 n ck www.datasheet.co.kr datasheet pdf - http://www..net/
rev. 0.2 / feb. 2010 34 speed bin table notes absolute specification (t oper ; v ddq = v dd = 1.5v +/- 0.075 v); notes: 1, the cl setting and cwl setting result in tck(av g).min and tck(avg).max requirements. when making a selection of tck (avg), both need to be fulfilled: requirements from cl setting as well as requirements from cwl setting. 2. tck(avg).min limits: since cas latency is not purely analog - data and strobe output are synchronized by the dll - all possible intermediate frequencies ma y not be guaranteed. an application should use the next smaller jedec standard tck (avg) value (2.5, 1. 875, 1.5, or 1.25 ns) when calculating cl [nck] = taa [ns] / tck (avg) [ns], rounding up to the next ?supported cl?. 3. tck(avg).max limits: calculate tck (avg) = taa. max / clselected and round the resulting tck (avg) down to the next valid speed bin (i.e. 3.3ns or 2.5ns or 1.875 ns or 1.25 ns). this result is tck(avg).max corresponding to clse lected. 4. ?reserved? settings are not allowed. user must program a different value. 5. any ddr3-1066 speed bin also supports functional op eration at lower frequencies as shown in the table which are not subject to production tests but verified by design/characterization. 6. any ddr3-1333 speed bin also supports functional op eration at lower frequencies as shown in the table which are not subject to production tests but verified by design/characterization. 7. any ddr3-1600 speed bin also supports functional oper ation at lower frequencie s as shown in the table which are not subject to production tests but verified by design/characterization. 8. hynix ddr3 sdram devices support down binning to cl=7 and cl=9, and taa/trcd/trp satisfy mini- mum value of 13.125 ns. spd settings are also prog rammed to match. for ex ample, ddr3 1333h devices supporting down binning to ddr3-1066f should program 13.125 ns in spd bytes for taamin (byte 16), trcdmin (byte 18), and trpmin (byte 20). ddr3-1600k devices supporting down binning to ddr3-1333h or ddr3 1600f should program 13.125 ns in spd bytes for taamin (byte 16), trcdmin (byte 18), and trp- min (byte 20). once trp (byte 20) is programmed to 13.125ns, trcmin (byte 21,23) also should be pro- grammed accordingly. for example, 49.125ns (trasm in + trpmin = 36 ns + 13.125 ns) for ddr3-1333h and 48.125ns (trasmin + trpmin = 35 ns + 13.125 ns) for ddr3-1600k. www.datasheet.co.kr datasheet pdf - http://www..net/
rev. 0.2 / feb. 2010 35 environmental parameters note : 1. stress greater than those listed may cause permanent damage to the device. this is a stress rating only, and device functional operation at or above the condit ions indicated is not implied. expousure to absolute maximum rating conditions for extended periods may affect reliablility. 2. up to 9850 ft. 3. the designer must meet the case temperature specifications for individual module components. symbol parameter rating units notes t opr operating temperature 0 to 65 o c1, 3 h opr operating humidity (relative) 10 to 90 % 1 t stg storage temperature -50 to +100 o c 1 h stg storage humidity (without condensation) 5 to 95 % 1 p bar barometric pressure (operating & storage) 105 to 69 k pascal 1, 2 www.datasheet.co.kr datasheet pdf - http://www..net/
rev. 0.2 / feb. 2010 36 pin capacitance (vdd=1.5v, vddq=1.5v) 1gb: HMT312S6BFR6C 2gb: hmt325s6bfr6c 2gb: hmt325s6bfr c 4gb: hmt351s6bfr8c note : 1. pins not under test are tied to gnd. 2. these value are guaranteed by design and tested on a sample basis only. pin symbol min max unit ck0, ck 0 c ck tbd tbd pf cke, odt, cs c ctrl tbd tbd pf address, ras , cas , we c i tbd tbd pf dq, dm, dqs, dqs c io tbd tbd pf pin symbol min max unit ck0, ck 0 c ck tbd tbd pf cke, odt, cs c ctrl tbd tbd pf address, ras , cas , we c i tbd tbd pf dq, dm, dqs, dqs c io tbd tbd pf pin symbol min max unit ck0, ck 0 c ck tbd tbd pf cke, odt, cs c ctrl tbd tbd pf address, ras , cas , we c i tbd tbd pf dq, dm, dqs, dqs c io tbd tbd pf pin symbol min max unit ck0, ck 0 c ck tbd tbd pf cke, odt, cs c ctrl tbd tbd pf address, ras , cas , we c i tbd tbd pf dq, dm, dqs, dqs c io tbd tbd pf www.datasheet.co.kr datasheet pdf - http://www..net/
rev. 0.2 / feb. 2010 37 idd and iddq specification pa rameters and test conditions idd and iddq measurement conditions in this chapter, idd and iddq measurement conditions such as test load and patt erns are defined. figure 1. shows the setup and test load for idd and iddq measurements. ? idd currents (such as idd0, idd1, idd2n, idd2nt , idd2p0, idd2p1, idd2q, idd3n, idd3p, idd4r, idd4w, idd5b, idd6, idd6et, idd6tc and idd7) are measured as time-averaged currents with all vdd balls of the ddr3 sdram under test tied togeth er. any iddq current is not included in idd cur- rents. ? iddq currents (such as iddq2nt and iddq4r) are measured as time-averaged currents with all vddq balls of the ddr3 sdram under test tied togeth er. any idd current is not included in iddq cur- rents. attention: iddq values cannot be directly used to calculate io power of the ddr3 sdram. they can be used to support correlation of simulated io powe r to actual io power as outlined in figure 2. in dram module application, iddq cannot be measured separately si nce vdd and vddq are using one merged-power layer in module pcb. for idd and iddq measurements, the following definitions apply: ? ?0? and ?low? is defined as vin <= v ilac(max). ? ?1? and ?high? is defined as vin >= v ihac(max). ? ?mid_level? is defined as inputs are vref = vdd/2. ? timing used for idd and iddq measurement-loop patterns are provided in table 1. ? basic idd and iddq measurement co nditions are described in table 2. ? detailed idd and iddq measurement-loop patte rns are described in table 3 through table 10. ? idd measurements are done after properly initializi ng the ddr3 sdram. this includes but is not lim- ited to setting ron = rzq/7 (34 ohm in mr1); qoff = 0 b (output buffer enabled in mr1); rtt_nom = rzq/6 (40 ohm in mr1); rtt_wr = rzq/2 (120 ohm in mr2); tdqs feature disabled in mr1 ? attention: the idd and iddq measurement-loop patterns need to be executed at least one time before actual idd or iddq measurement is started. ? define d = {cs , ras , cas , we }:= {high, low, low, low} define d = {cs , ras , cas , we }:= {high, high, high, high} www.datasheet.co.kr datasheet pdf - http://www..net/
rev. 0.2 / feb. 2010 38 figure 1 - measurement setup and test load for idd and iddq (optional) measurements [note: dimm level output test load condition may be different from above figure 2 - correlation from simulated channel io power to actual ch annel io power supported by iddq measurement v dd ddr3 sdram v ddq reset ck/ck dqs, dqs cs ras , cas , we a, ba odt zq v ss v ssq dq, dm, tdqs, tdqs cke r tt = 25 ohm v ddq /2 i dd i ddq (optional) application specific memory channel environment channel io power simulation iddq simulation iddq simulation channel io power number iddq test load correction www.datasheet.co.kr datasheet pdf - http://www..net/
rev. 0.2 / feb. 2010 39 table 1 -timings used for idd an d iddq measurement-loop patterns table 2 -basic idd and id dq measurement conditions symbol ddr3-1066 ddr3-1333 ddr3-1600 unit 7-7-7 9-9-9 11-11-11 t ck 1.875 1.5 1.25 ns cl 7 9 11 nck n rcd 7911nck n rc 27 33 39 nck n ras 20 24 28 nck n rp 7911nck n faw 1kb page size 20 20 24 nck 2kb page size 27 30 32 nck n rrd 1kb page size 4 4 5 nck 2kb page size 6 5 6 nck n rfc -512mb 48 60 72 nck n rfc -1 gb 59 74 88 nck n rfc - 2 gb 86 107 128 nck n rfc - 4 gb 160 200 240 nck n rfc - 8 gb 187 234 280 nck symbol description i dd0 operating one bank active-precharge current cke: high; external clock: on; tck, nrc, nras, cl: see table 1; bl: 8 a) ; al: 0; cs : high between act and pre; command, address, bank address inputs: partiall y toggling according to table 3; data io: mid-level; dm: stable at 0; bank activity: cycl ing with one bank active at a time: 0,0,1,1,2,2,... (see table 3); output buffer and rtt: enabled in mode registers b) ; odt signal: stable at 0; pattern details: see table 3. i dd1 operating one bank active-precharge current cke: high; external clock: on; tck, n rc, nras, nrcd, cl: see table 1; bl: 8 a) ; al: 0; cs : high between act, rd and pre; command, address; bank address inputs, da ta io: partially toggling ac cording to table 4; dm: stable at 0; bank activity: cycling with on bank active at a time: 0,0,1,1,2,2,... (see table 4); output buffer and rtt: enabled in mode registers b) ; odt signal: stable at 0; pattern details: see table 4. www.datasheet.co.kr datasheet pdf - http://www..net/
rev. 0.2 / feb. 2010 40 i dd2n precharge standby current cke: high; external clock: on ; tck, cl: see table 1; bl: 8 a) ; al: 0; cs : stable at 1; command, address, bank address inputs: partially toggling accord ing to table 5; data io: mid_level; dm: stable at 0; bank activity: all banks closed; output buffer and rtt: enabled in mode registers b) ; odt signal: stable at 0; pattern details: see table 5. i dd2nt precharge standby odt current cke: high; external clock: on ; tck, cl: see table 1; bl: 8 a) ; al: 0; cs : stable at 1; command, address, bank address inputs: partially toggling accord ing to table 6; data io: mid_level; dm: stable at 0; bank activity: all banks closed; output buffer and rtt: enabled in mode registers b) ; odt signal: toggling according to table 6; pattern details: see table 6. i dd2p0 precharge power-down current slow exit cke: low; external clock: on ; tck, cl: see table 1; bl: 8 a) ; al: 0; cs : stable at 1; command, address, bank address inputs: stable at 0; data io: mid_level; dm: st able at 0; bank activity: all banks closed; output buffer and rtt: enabled in mode registers b) ; odt signal: stable at 0; pr echarge power down mode: slow exit c) i dd2p1 precharge power-down current fast exit cke: low; external clock: on ; tck, cl: see table 1; bl: 8 a) ; al: 0; cs : stable at 1; command, address, bank address inputs: stable at 0; data io: mid_level; dm: st able at 0; bank activity: all banks closed; output buffer and rtt: enabled in mode registers b) ; odt signal: stable at 0; precharge power down mode: fast exit c) i dd2q precharge quiet standby current cke: high; external clock: on ; tck, cl: see table 1; bl: 8 a) ; al: 0; cs : stable at 1; command, address, bank address inputs: stable at 0; data io: mid_level; dm: stable at 0; bank activity: all banks closed; output buffer and rtt: enabled in mode registers b) ; odt signal: stable at 0 i dd3n active standby current cke: high; external clock: on ; tck, cl: see table 1; bl: 8 a) ; al: 0; cs : stable at 1; command, address, bank address inputs: partially toggling accord ing to table 5; data io: mid_level; dm: stable at 0; bank activity: all banks open; output buffer and rt t: enabled in mode registers b) ; odt signal: stable at 0; pattern details: see table 5. i dd3p active power-down current cke: low; external clock: on ; tck, cl: see table 1; bl: 8 a) ; al: 0; cs : stable at 1; command, address, bank address inputs: stable at 0; data io: mid_level; dm: stable at 0; bank activity: all banks open; output buffer and rtt: enabled in mode registers b) ; odt signal: stable at 0 symbol description www.datasheet.co.kr datasheet pdf - http://www..net/
rev. 0.2 / feb. 2010 41 i dd4r operating burst read current cke: high; external clock: on ; tck, cl: see table 1; bl: 8 a) ; al: 0; cs : high between rd; command, address, bank address inputs: partially toggling according to tabl e 7; data io: seamless read data burst with different data between one burst and the next one according to tabl e 7; dm: stable at 0; bank activity: all banks open, rd commands cycling through banks: 0,0,1,1,2,2,...(see table 7); output buffer and rtt: enabled in mode registers b) ; odt signal: stable at 0; pattern details: see table 7. i dd4w operating burst write current cke: high; external clock: on ; tck, cl: see table 1; bl: 8 a) ; al: 0; cs : high between wr; command, address, bank address inputs: partially toggling according to tabl e 8; data io: seamless read data burst with different data between one burst and the next one according to tabl e 8; dm: stable at 0; bank activity: all banks open, wr commands cycling through banks: 0,0,1,1,2,2,...(see table 8); output buffer and rtt: enabled in mode registers b) ; odt signal: stable at high ; pattern details: see table 8. i dd5b burst refresh current cke: high; external clock: on; tck, cl, nrfc: see table 1; bl: 8 a) ; al: 0; cs : high between ref; command, address, bank address inputs: partiall y toggling according to table 9; data io: mid_level; dm: stable at 0; bank activity: ref command every nref (see table 9); output buffer and rtt: enabled in mode registers b) ; odt signal: stable at 0; pattern details: see table 9. i dd6 self-refresh current: normal temperature range t case : 0 - 85 o c; auto self-refresh (asr): disabled d) ;self-refresh temperature range (srt): normal e) ; cke: low; external clock: off; ck and ck : low; cl: see table 1; bl: 8 a) ; al: 0; cs , command, address, bank address inputs, data io: mid_level; dm: stable at 0; bank activity: self-refresh operation; output buffer and rtt: enabled in mode registers b) ; odt signal: mid_level i dd6et self-refresh current: extended temperature range t case : 0 - 95 o c; auto self-refresh (asr): disabled d) ;self-refresh temperature range (srt): extended e) ; cke: low; external clock: off; ck and ck : low; cl: see table 1; bl: 8 a) ; al: 0; cs , command, address, bank address inputs, data io: mid_level; dm: stable at 0; bank activity: extended temperature self-refresh operation; output buffer and rtt: enabled in mode registers b) ; odt signal: mid_level symbol description www.datasheet.co.kr datasheet pdf - http://www..net/
rev. 0.2 / feb. 2010 42 a) burst length: bl8 fixed by mrs: set mr0 a[1,0]=00b b) output buffer enable: set mr1 a[12] = 0b; set mr1 a[5,1] = 01b; rtt_nom enable: set mr1 a[9,6,2] = 011b; rtt_wr enable: set mr2 a[10,9] = 10b c) precharge power down mode: set mr0 a12=0b for slow exit or mr0 a12 = 1b for fast exit d) auto self-refresh (asr): set mr2 a6 = 0b to disable or 1b to enable feature e) self-refresh temperature range (srt): set mr2 a7 = 0b for normal or 1b for extended temperature range f) read burst type: nibble sequential, set mr0 a[3] = 0b i dd6tc auto self-refresh current t case : 0 - 95 o c; auto self-refresh (asr): enabled d) ;self-refresh temperature range (srt): normal e) ; cke: low; external clock: off; ck and ck : low; cl: see table 1; bl: 8 a) ; al: 0; cs , command, address, bank address inputs, data io: mid_level; dm: stable at 0; bank activity: auto self-r efresh operation; output buffer and rtt: enabled in mode registers b) ; odt signal: mid_level i dd7 operating bank interleave read current cke: high; external clock: on; tck, nrc, nr as, nrcd, nrrd, nfaw, cl: see table 1; bl: 8 a,f) ; al: cl-1; cs : high between act and rda; command, address, bank a ddress inputs: partially togg ling according to table 10; data io: read data burst with different data betw een one burst and the next one according to table 10; dm: stable at 0; bank activity: two times interleaved cycling through banks (0, 1,.. .7) with different address- ing, wee table 10; output buffer an d rtt: enabled in mode registers b) ; odt signal: stable at 0; pattern details: see table 10. symbol description www.datasheet.co.kr datasheet pdf - http://www..net/
rev. 0.2 / feb. 2010 43 table 3 - idd0 measurement-loop pattern a) a) dm must be driven low all the time. dqs, dqs are mid-level. b) dq signals are mid-level. ck, ck cke sub-loop cycle number command cs ras cas we odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data b) toggling static high 0 0 act0011000000 00 - 1,2 d, d1000000000 00 - 3,4 d , d 1111000000 00 - ... repeat pattern 1...4 until nras - 1, truncate if necessary nras pre0010000000 00 - ... repeat pattern 1...4 until n rc - 1, truncate if necessary 1*nrc+0 act 0 0 1 1 0 0 00 0 0 f 0 - 1*nrc+1, 2 d, d 1 0 0 0 0 0 00 0 0 f 0 - 1*nrc+3, 4 d , d 1111000000 f0 - ... repeat pattern 1...4 until 1*nrc + nras - 1, truncate if necessary 1*nrc+nras pre 0 0 1 0 0 0 00 0 0 f 0 - ... repeat pattern 1...4 until 2*nrc - 1, truncate if necessary 1 2*nrc repeat sub-loop 0, use ba[2:0] = 1 instead 2 4*nrc repeat sub-loop 0, use ba[2:0] = 2 instead 3 6*nrc repeat sub-loop 0, use ba[2:0] = 3 instead 4 8*nrc repeat sub-loop 0, use ba[2:0] = 4 instead 5 10*nrc repeat sub-loop 0, use ba[2:0] = 5 instead 6 12*nrc repeat sub-loop 0, use ba[2:0] = 6 instead 7 14*nrc repeat sub-loop 0, use ba[2:0] = 7 instead www.datasheet.co.kr datasheet pdf - http://www..net/
rev. 0.2 / feb. 2010 44 table 4 - idd1 measurement-loop pattern a) a) dm must be driven low all the time. dqs, dqs are used according to rd commands, otherwise mid- level. b) burst sequence driven on each dq signal by re ad command. outside burst operation, dq signals are mid_level. ck, ck cke sub-loop cycle number command cs ras cas we odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data b) toggling static high 0 0 act 0 0 1 1 0 0 00 0 0 0 0 - 1,2 d, d 1 0 0 0 0 0 00 0 0 0 0 - 3,4 d , d 1111 0 00000 0 0 - ... repeat pattern 1...4 until nrcd - 1, truncate if necessary nrcd rd 0 1 0 1 0 0 00 0 0 0 0 00000000 ... repeat pattern 1...4 until nras - 1, truncate if necessary nras pre 0 0 1 0 0 0 00 0 0 0 0 - ... repeat pattern 1...4 until nr c - 1, truncate if necessary 1*nrc+0 act 0 0 1 1 0 0 00 0 0 f 0 - 1*nrc+1,2 d, d 1 0 0 0 0 0 00 0 0 f 0 - 1*nrc+3,4 d , d 1111 0 00000 f 0 - ... repeat pattern nrc + 1,. ..4 until nrc + nrce - 1, truncate if necessary 1*nrc+nrcd rd 0 1 0 1 0 0 00 0 0 f 0 00110011 ... repeat pattern nrc + 1, ...4 until nrc + nras - 1, truncate if necessary 1*nrc+nras pre 0 0 1 0 0 0 00 0 0 f 0 - ... repeat pattern nrc + 1, ...4 until *2 nrc - 1, truncate if necessary 1 2*nrc repeat sub-loop 0, use ba[2:0] = 1 instead 2 4*nrc repeat sub-loop 0, use ba[2:0] = 2 instead 3 6*nrc repeat sub-loop 0, use ba[2:0] = 3 instead 4 8*nrc repeat sub-loop 0, use ba[2:0] = 4 instead 5 10*nrc repeat sub-loop 0, use ba[2:0] = 5 instead 6 12*nrc repeat sub-loop 0, use ba[2:0] = 6 instead 7 14*nrc repeat sub-loop 0, use ba[2:0] = 7 instead www.datasheet.co.kr datasheet pdf - http://www..net/
rev. 0.2 / feb. 2010 45 table 5 - idd2n and idd3n measurement-loop pattern a) a) dm must be driven low all the time. dqs, dqs are mid-level. b) dq signals are mid-level. table 6 - idd2nt and iddq2n t measurement-loop pattern a) a) dm must be driven low all the time. dqs, dqs are mid-level. b) dq signals are mid-level. ck, ck cke sub-loop cycle number command cs ras cas we odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data b) toggling static high 0 0 d 10000000000 - 1 d 10000000000 - 2d 111100000f0 - 3d 111100000f0 - 1 4-7 repeat sub-loop 0, use ba[2:0] = 1 instead 2 8-11 repeat sub-loop 0, use ba[2:0] = 2 instead 3 12-15 repeat sub-loop 0, use ba[2:0] = 3 instead 4 16-19 repeat sub-loop 0, use ba[2:0] = 4 instead 5 20-23 repeat sub-loop 0, use ba[2:0] = 5 instead 6 24-17 repeat sub-loop 0, use ba[2:0] = 6 instead 7 28-31 repeat sub-loop 0, use ba[2:0] = 7 instead ck, ck cke sub-loop cycle number command cs ras cas we odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data b) toggling static high 0 0 d10000000000 - 1d10000000000- 2d 1111 0 0 0 0 0 f 0 - 3d 1111 0 0 0 0 0 f 0 - 1 4-7 repeat sub-loop 0, but odt = 0 and ba[2:0] = 1 2 8-11 repeat sub-loop 0, but odt = 1 and ba[2:0] = 2 3 12-15 repeat sub-loop 0, but odt = 1 and ba[2:0] = 3 4 16-19 repeat sub-loop 0, but odt = 0 and ba[2:0] = 4 5 20-23 repeat sub-loop 0, but odt = 0 and ba[2:0] = 5 6 24-17 repeat sub-loop 0, but odt = 1 and ba[2:0] = 6 7 28-31 repeat sub-loop 0, but odt = 1 and ba[2:0] = 7 www.datasheet.co.kr datasheet pdf - http://www..net/
rev. 0.2 / feb. 2010 46 table 7 - idd4r and iddq4r measurement-loop pattern a) a) dm must be driven low all the time. dqs, dqs are used according to rd commands, otherwise mid-level. b) burst sequence driven on each dq signal by read co mmand. outside burst operation, dq signals are mid-level. table 8 - idd4w measurement-loop pattern a) a) dm must be driven low all the time. dqs, dqs are used according to wr commands, otherwise mid-level. b) burst sequence driven on each dq signal by write co mmand. outside burst operation, dq signals are mid-level. ck, ck cke sub-loop cycle number command cs ras cas we odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data b) toggling static high 0 0 rd 0 1 0 1 0 0 00 0 0 0 0 00000000 1d100000000000- 2,3 d ,d 1111 0 0000 0 0 0 - 4 rd 0 1 0 1 0 0 00 0 0 f 0 00110011 5d1000000000f0- 6,7 d ,d 1111 0 0000 0 f 0 - 1 8-15 repeat sub-loop 0, but ba[2:0] = 1 2 16-23 repeat sub-loop 0, but ba[2:0] = 2 3 24-31 repeat sub-loop 0, but ba[2:0] = 3 4 32-39 repeat sub-loop 0, but ba[2:0] = 4 5 40-47 repeat sub-loop 0, but ba[2:0] = 5 6 48-55 repeat sub-loop 0, but ba[2:0] = 6 7 56-63 repeat sub-loop 0, but ba[2:0] = 7 ck, ck cke sub-loop cycle number command cs ras cas we odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data b) toggling static high 0 0 wr 0 1 0 0 1 0 00 0 0 0 0 00000000 1d100010000000- 2,3 d ,d 1111 1 0000 0 0 0 - 4 wr 0 1 0 0 1 0 00 0 0 f 0 00110011 5d1000100000f0- 6,7 d ,d 1111 1 0000 0 f 0 - 1 8-15 repeat sub-loop 0, but ba[2:0] = 1 2 16-23 repeat sub-loop 0, but ba[2:0] = 2 3 24-31 repeat sub-loop 0, but ba[2:0] = 3 4 32-39 repeat sub-loop 0, but ba[2:0] = 4 5 40-47 repeat sub-loop 0, but ba[2:0] = 5 6 48-55 repeat sub-loop 0, but ba[2:0] = 6 7 56-63 repeat sub-loop 0, but ba[2:0] = 7 www.datasheet.co.kr datasheet pdf - http://www..net/
rev. 0.2 / feb. 2010 47 table 9 - idd5b measur ement-loop pattern a) a) dm must be driven low all the time. dqs, dqs are mid-level. b) dq signals are mid-level. ck, ck cke sub-loop cycle number command cs ras cas we odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data b) toggling static high 0 0 ref 0 0 0 1 0 0 0 0 0 0 0 - 11.2 d, d 1 0 0 0 0 0 00 0 0 0 0 - 3,4 d , d 1111 0 0000 0 f 0 - 5...8 repeat cycles 1...4, but ba[2:0] = 1 9...12 repeat cycles 1...4, but ba[2:0] = 2 13...16 repeat cycles 1...4, but ba[2:0] = 3 17...20 repeat cycles 1...4, but ba[2:0] = 4 21...24 repeat cycles 1...4, but ba[2:0] = 5 25...28 repeat cycles 1...4, but ba[2:0] = 6 29...32 repeat cycles 1...4, but ba[2:0] = 7 2 33...nrfc-1 repeat sub-loop 1, until nrfc - 1. truncate, if necessary. www.datasheet.co.kr datasheet pdf - http://www..net/
rev. 0.2 / feb. 2010 48 table 10 - idd7 meas urement-loop pattern a) attention! sub-loops 10-19 have inverse a[6:3] pattern and data pattern than sub-loops 0-9 a) dm must be driven low all the time. dqs, dqs are used according to rd commands, otherwise mid-level. b) burst sequence driven on each dq signal by read co mmand. outside burst operation, dq signals are mid-level. ck, ck cke sub-loop cycle number command cs ras cas we odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data b) toggling static high 00 act 0 0 1 1 0 0 00 0 0 0 0 - 1 rda 0 1 0 1 0 0 00 1 0 0 0 00000000 2d100000000000- ... repeat above d command until nrrd - 1 1 nrrd act 0 0 1 1 0 1 00 0 0 f 0 - nrrd+1 rda 0 1 0 1 0 1 00 1 0 f 0 00110011 nrrd+2 d 1 0 0 0 0 1 00 0 0 f 0 - ... repeat above d command until 2* nrrd - 1 2 2*nrrd repeat sub-loop 0, but ba[2:0] = 2 3 3*nrrd repeat sub-loop 1, but ba[2:0] = 3 4 4*nrrd d1000030000f0 - assert and repeat abov e d command until nfaw - 1, if necessary 5 nfaw repeat sub-loop 0, but ba[2:0] = 4 6 nfaw+nrrd repeat sub-loop 1, but ba[2:0] = 5 7 nfaw+2*nrrd repeat sub-loop 0, but ba[2:0] = 6 8 nfaw+3*nrrd repeat sub-loop 1, but ba[2:0] = 7 9 nfaw+4*nrrd d1000070000f0 - assert and repeat abov e d command until 2* nfaw - 1, if necessary 10 2*nfaw+0 act 0 0 1 1 0 0 00 0 0 f 0 - 2*nfaw+1 rda 0 1 0 1 0 0 00 1 0 f 0 00110011 2&nfaw+2 d1000000000f0 - repeat above d command until 2* nfaw + nrrd - 1 11 2*nfaw+nrrd act 0 0 1 1 0 1 00 0 0 0 0 - 2*nfaw+nrrd+1 rda 0 1 0 1 0 1 00 1 0 0 0 00000000 2&nfaw+nrrd+2 d100001000000 - repeat above d command until 2* nfaw + 2* nrrd - 1 12 2*nfaw+2*nrrd repeat sub- loop 10, but ba[2:0] = 2 13 2*nfaw+3*nrrd repeat sub- loop 11, but ba[2:0] = 3 14 2*nfaw+4*nrrd d100003000000- assert and repeat abov e d command until 3* nfaw - 1, if necessary 15 3*nfaw repeat sub-loop 10, but ba[2:0] = 4 16 3*nfaw+nrrd repeat sub-loop 11, but ba[2:0] = 5 17 3*nfaw+2*nrrd repeat sub- loop 10, but ba[2:0] = 6 18 3*nfaw+3*nrrd repeat sub- loop 11, but ba[2:0] = 7 19 3*nfaw+4*nrrd d100007000000- assert and repeat abov e d command until 4* nfaw - 1, if necessary www.datasheet.co.kr datasheet pdf - http://www..net/
rev. 0.2 / feb. 2010 49 idd specifications (tcase: 0 to 95 o c) * module idd values in the datasheet are only a calculation based on the component idd spec. the actual measurements may vary according to dq loading cap. 1gb, 128m x 64 so-d imm: HMT312S6BFR6C 2gb, 256m x 64 so-d imm: hmt325s6bfr6c symbol ddr3 1066 ddr3 1333 ddr3 1600 unit note idd0 240 260 260 ma idd1 280 300 300 ma idd2n 100 120 120 ma idd2nt 140 160 180 ma idd2p0 48 48 48 ma idd2p1 60 60 60 ma idd2q 100 120 120 ma idd3n 120 120 160 ma idd3p 60 60 60 ma idd4r 420 520 560 ma idd4w 420 520 600 ma idd5b 600 620 640 ma idd6 48 48 48 ma idd6et 60 60 60 ma idd6tc 60 60 60 ma idd7 520 680 720 ma symbol ddr3 1066 ddr3 1333 ddr3 1600 unit note idd0 340 380 380 ma idd1 380 420 420 ma idd2n 200 240 240 ma idd2nt 280 320 360 ma idd2p0 96 96 96 ma idd2p1 120 120 120 ma idd2q 200 240 240 ma idd3n 240 240 320 ma idd3p 120 120 120 ma idd4r 520 640 680 ma idd4w 520 640 720 ma idd5b 700 740 760 ma idd6 96 96 96 ma idd6et 120 120 120 ma idd6tc 120 120 120 ma idd7 620 800 840 ma www.datasheet.co.kr datasheet pdf - http://www..net/
rev. 0.2 / feb. 2010 50 2gb, 256m x 64 so-d imm: hmt325s6bfr8c 4gb, 512m x 64 so-d imm: hmt351s6bfr8c symbol ddr3 1066 ddr3 1333 ddr3 1600 unit note idd0 360 400 440 ma idd1 440 480 520 ma idd2n 200 240 240 ma idd2nt 256 280 320 ma idd2p0 96 96 96 ma idd2p1 120 120 120 ma idd2q 200 240 240 ma idd3n 240 280 320 ma idd3p 120 120 120 ma idd4r 640 760 840 ma idd4w 640 760 880 ma idd5b 1200 1240 1280 ma idd6 96 96 96 ma idd6et 120 120 120 ma idd6tc 120 120 120 ma idd7 880 1080 1160 ma symbol ddr3 1066 ddr3 1333 ddr3 1600 unit note idd0 560 640 760 ma idd1 640 720 840 ma idd2n 400 480 480 ma idd2nt 512 560 640 ma idd2p0 192 192 192 ma idd2p1 240 240 240 ma idd2q 400 480 480 ma idd3n 480 560 640 ma idd3p 240 240 240 ma idd4r 840 1000 1160 ma idd4w 840 1000 1200 ma idd5b 1400 1480 1600 ma idd6 192 192 192 ma idd6et 240 240 240 ma idd6tc 240 240 240 ma idd7 1081 1320 1480 ma www.datasheet.co.kr datasheet pdf - http://www..net/
rev. 0.2 / feb. 2010 51 module dimensions 128mx64 - HMT312S6BFR6C front back spd 30.0mm 67.60mm 20.0mm 6.00 2.0 21.00 39.00 2.15 3.00 pin 1 pin 203 detail-a 3.80mm max 4.00 0.10 1.65 0.10 1.00 mm 0.08 1.80 0.10 2 x note : 1. tolerance on all dimensions unless otherwise stated. units: millimeters side 2.55 1.00 detail of contacts a 0.3 0.3~1.0 0.15 0.05 0.45 0.03 4.00 0.10 0.60 www.datasheet.co.kr datasheet pdf - http://www..net/
rev. 0.2 / feb. 2010 52 256mx64 - hmt325s6bfr6c front back spd 30.0mm 67.60mm 20.0mm 6.00 2.0 21.00 39.00 2.15 3.00 pin 1 pin 203 detail-a 3.80mm max 4.00 0.10 1.65 0.10 1.00 mm 0.08 1.80 0.10 2 x note : 1. tolerance on all dimensions unless otherwise stated. units: millimeters side 2.55 1.00 detail of contacts a 0.3 0.3~1.0 0.15 0.05 0.45 0.03 4.00 0.10 0.60 www.datasheet.co.kr datasheet pdf - http://www..net/
rev. 0.2 / feb. 2010 53 256mx64 - hmt325s6bfr8c front back spd 30.0mm 67.60mm 20.0mm 6.00 2.0 21.00 39.00 2.15 3.00 pin 1 pin 203 detail-a 3.80mm max 4.00 0.10 1.65 0.10 1.00 mm 0.08 1.80 0.10 2 x note : 1. tolerance on all dimensions unless otherwise stated. units: millimeters side 2.55 1.00 detail of contacts a 0.3 0.3~1.0 0.15 0.05 0.45 0.03 4.00 0.10 0.60 www.datasheet.co.kr datasheet pdf - http://www..net/
rev. 0.2 / feb. 2010 54 512mx64 - hmt351s6bfr8c front back 30.0mm 67.60mm 20.0mm 6.00 2.0 21.00 39.00 2.15 3.00 pin 1 pin 203 detail- a spd 3.80mm max detail-b 4.00 0.10 1.65 0.10 1.00 mm 0.08 1.80 0.10 2 x side note : 1. tolerance on al l dimensions unless otherwise stated. units: millimeters 2.55 1.00 detail of contacts a 0.3 0.3~1.0 0.15 0.05 0.45 0.03 4.00 0.10 0.60 www.datasheet.co.kr datasheet pdf - http://www..net/

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